The use of PLLs in communications over the years has become an ever-growing trend. New applications with specific synchronization requirements are demanding complex and flexible PLLs. Economic and integration reasons are pushing for support of multiple application scenarios, each requiring different standard prescribing synchronization clock criteria. User configurable flexibility has become an important requirement for new PLLs.
Synchronization clocks generated by PLLs are required to meet certain criteria for amount of phase and frequency change over prescribed time interval. While older telecom standards required relatively relaxed criteria for phase and frequency slope limits, new requirements, mainly driven by Timing over Packet switched network (ToP), are a couple of orders of magnitude tighter. The maximum allowed value for phase slope and frequency slope of any given clock is mainly determined by the ability of down-stream equipment to adjust its rate such that bit-errors are avoided following reference re-arrangement or either phase or frequency transients on the PLL's reference inputs.
To be able to effectively limit phase change behavior of a type 2 Phase Locked Loop (PLL) (namely a PLL that eliminates phase difference between its input and output upon either frequency or phase changes at its input), it has to be understood that the output clock phase consists of proportional (P) and integral (I) parts. The sum of the proportional and integral parts of the output clock phase change over a specified time has to be limited to a prescribed value. Also, it is important to understand that time required to withstand a prescribed phase slope limit by a PLL output is directly proportional to the maximum phase offset between the PLL's input and output that the PLL is required to withstand.
In the prior art, as is shown in FIG. 1, phase slope limiting is mainly taken care by limiting the proportional part of the PLL phase error whenever the phase difference between the PLL's input and output exceeds a certain threshold. This allows the PLL to maintain the same architecture and structure when used in phase slope limiting mode as when in normal non-limiting mode of operation. In order to meet the overall prescribed phase slope limit, two approaches are commonly adopted.
In the first approach, depending on the PLL bandwidth and damping factor, the proportional part is significantly over-limited such that after the specified time, which is proportional to the maximum phase error the PLL is required to withstand, the sum of proportional and integral part does not exceed prescribed phase slope limit. The disadvantage of this approach is a slowdown in PLL response time since at the beginning of the limiting process, when the accumulated integral part is small, the output phase changes are significantly smaller than the prescribed phase slope limit. Knowing that the change of integral part has an exponential characteristic, increasing the maximum phase error that the PLL is required to withstand for a particular application requires decreasing the proportional phase limit to the point where it no longer can be used.
The second approach involves freezing the integral part of the output clock phase and limiting the proportional part to a prescribed phase slope limit for a specified time so that the overall output clock phase slope limit can be maintained. The downside of this approach, which requires integral part to be frozen, lies in its inability to follow frequency changes since the integral part is responsible for frequency change compensation. In addition, after releasing the PLL from limiting to non-limiting phase slope mode, the PLL has to make frequency and phase adjustments in order to catch up with potential input frequency changes occurring while in the phase slope limiting mode.
The most common approach for limiting frequency change over a specified time (frequency slope) to a prescribed value, used in previous PLL implementations, is shown in FIGS. 2 and 3.
In this approach, the DCO frequency Fd change is simply limited to a prescribed FSL limit when the difference between the current and previous value exceeds the limit. The downside of this approach lies in the fact that the PLL may become unstable due to slow response to fast frequency changes with constant limiting.